1. Technical Field
This disclosure relates to electronic design automation (EDA). More specifically, this disclosure relates to identifying candidate nets for buffering using numerical methods.
2. Related Art
Insertion of repeaters on wires can dramatically reduce the delay from the driver of a net to one or more of its sinks. The related optimization problem (referred to as buffering or repeater insertion) is well known and many different approaches have been proposed for solving the optimization problem. Unfortunately, conventional approaches assume that a net (wire) that requires buffering has been identified and the only problem is to determine an optimal buffering solution. Furthermore, all nets do not benefit from repeater insertion. Although long wires can benefit from repeater insertion, other wires can actually degrade in delay when they are buffered. Indeed, for such wires, some conventional buffering approaches find that the no-buffer solution is optimal. However, in conventional approaches, such a “no-buffer solution is optimal” determination is only arrived at once the approach completes its computation. Consequently, conventional approaches tend to spend the same amount of time performing buffering computations even if no buffering is eventually performed (because the approach determines that the no buffering solution is optimal).
In addition, many conventional buffering approaches have a two phase approach, wherein in the first phase they construct a buffer topology, and in the second phase they size the buffers associated with the constructed topology. Most of the run-time of such conventional approaches is spent during the second phase, i.e., buffer sizing phase.
What are needed are systems and techniques for performing fast and accurate buffering (also known as repeater insertion).